1. Field of the Invention
An aspect of the present invention relates to a semiconductor device having a plurality of power domains.
2. Description of the Related Art
A system large scale integrated circuit (LSI), a system-on-a-chip (SoC), or a multi-chip package (MCP), which serves as a semiconductor device, is provided with circuit portions respectively belonging to a plurality of power domains that differ from one another. As the micromachining of semiconductor elements progresses, the number of elements integrated on a system LSI, a SoC, or an MCP and the number of circuit portions mounted thereon increase. Further, the need for use of the separated power domains increases. In a conventional semiconductor device having a plurality of separated power domains, an electrostatic discharge (ESD) protection countermeasure is needed for each of circuit portions that are independent in power supplies of one another (see, e.g., JP-2004-119883-A).
In the conventional semiconductor device described in, e.g., JP-2004-119883-A, the gate withstand voltage of a transistor of a second circuit portion belonging to a second power domain, to which a first signal output from a first circuit portion belonging to a first power domain is input, is set to be higher than that of each of other transistors thereof. As a result, the ESD withstanding capability of the second circuit portion is enhanced.
However, in the conventional semiconductor device, since a high gate-withstand-voltage transistor that is lower in the driving capability than the other transistors is provided at an input side of the second circuit portion, the characteristic of the second circuit portion is degraded.